Unified Coverage Report :: Group :: router_pkg::router_coverage::cg_register

Group : router_pkg::router_coverage::cg_register_fields

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
75.00	75.00	1	100	1	1	64	64

Source File(s) :
/scratch/cs199-buw/UVM_Practice/Router_UVM/env/router_coverage.svh

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
register_fields_cg	75.00	1	100	1	64	64

Summary for Group router_pkg::router_coverage::cg_register_fields

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	83.33
Crosses	4	2	2	50.00

Variables for Group router_pkg::router_coverage::cg_register_fields

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_global_enable	2	1	1	50.00	100	1	1	0
cp_priority	2	0	2	100.00	100	1	1	0
cp_priority_transitions	4	0	4	100.00	100	1	1	0

Crosses for Group router_pkg::router_coverage::cg_register_fields

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_enable_priority	4	2	2	50.00	100	1	1	0

Group Instance : register_fields_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

Summary for Group Instance register_fields_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	83.33
Crosses	4	2	2	50.00

Variables for Group Instance register_fields_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_global_enable	2	1	1	50.00	100	1	1	0
cp_priority	2	0	2	100.00	100	1	1	0
cp_priority_transitions	4	0	4	100.00	100	1	1	0

Crosses for Group Instance register_fields_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_enable_priority	4	2	2	50.00	100	1	1	0

Summary for Variable cp_global_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_global_enable

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
disabled	0	1	1

Covered bins

NAME	COUNT	AT LEAST
enabled	1744	1

Summary for Variable cp_priority

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_priority

Bins

NAME	COUNT	AT LEAST
port_b_priority	602	1
port_a_priority	1142	1

Summary for Variable cp_priority_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_priority_transitions

Bins

NAME	COUNT	AT LEAST
stays_b	601	1
stays_a	1140	1
b_to_a	1	1
a_to_b	1	1

Summary for Cross cross_enable_priority

Samples crossed: cp_global_enable cp_priority

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cross_enable_priority

Element holes

cp_global_enable	cp_priority	COUNT	AT LEAST	NUMBER
[disabled]	*	--	--	2

Covered bins

cp_global_enable	cp_priority	COUNT	AT LEAST
enabled	port_b_priority	602	1
enabled	port_a_priority	1142	1

Summary for Variable cp_global_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_global_enable

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
disabled	0	1	1

Covered bins

NAME	COUNT	AT LEAST
enabled	1744	1

Summary for Variable cp_priority

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_priority

Bins

NAME	COUNT	AT LEAST
port_b_priority	602	1
port_a_priority	1142	1

Summary for Variable cp_priority_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_priority_transitions

Bins

NAME	COUNT	AT LEAST
stays_b	601	1
stays_a	1140	1
b_to_a	1	1
a_to_b	1	1

Summary for Cross cross_enable_priority

Samples crossed: cp_global_enable cp_priority

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cross_enable_priority

Element holes

cp_global_enable	cp_priority	COUNT	AT LEAST	NUMBER
[disabled]	*	--	--	2

Covered bins

cp_global_enable	cp_priority	COUNT	AT LEAST
enabled	port_b_priority	602	1
enabled	port_a_priority	1142	1