Unified Coverage Report :: Group :: router_pkg::router_coverage::cg_port_a

Group : router_pkg::router_coverage::cg_port_a_transactions

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
72.50	72.50	1	100	1	1	64	64

Source File(s) :
/scratch/cs199-buw/UVM_Practice/Router_UVM/env/router_coverage.svh

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb_top.me.obj.cg_port_a_transactions	72.50	1	100	1	64	64

Summary for Group router_pkg::router_coverage::cg_port_a_transactions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	2	11	75.00
Crosses	28	7	21	67.50

Variables for Group router_pkg::router_coverage::cg_port_a_transactions

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_port_a_valid	2	1	1	50.00	100	1	1	0
cp_data_a	5	0	5	100.00	100	1	1	0
cp_addr_a	4	0	4	100.00	100	1	1	0
cp_ready_a	2	1	1	50.00	100	1	1	0

Crosses for Group router_pkg::router_coverage::cg_port_a_transactions

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_addr_data	20	3	17	85.00	100	1	1	0
cross_addr_ready	8	4	4	50.00	100	1	1	0

Group Instance : tb_top.me.obj.cg_port_a_transactions

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.50	1	100	1	64	64

Summary for Group Instance tb_top.me.obj.cg_port_a_transactions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	2	11	75.00
Crosses	28	7	21	67.50

Variables for Group Instance tb_top.me.obj.cg_port_a_transactions

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_port_a_valid	2	1	1	50.00	100	1	1	0
cp_data_a	5	0	5	100.00	100	1	1	0
cp_addr_a	4	0	4	100.00	100	1	1	0
cp_ready_a	2	1	1	50.00	100	1	1	0

Crosses for Group Instance tb_top.me.obj.cg_port_a_transactions

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_addr_data	20	3	17	85.00	100	1	1	0
cross_addr_ready	8	4	4	50.00	100	1	1	0

Summary for Variable cp_port_a_valid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_port_a_valid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST
valid	872	1

Summary for Variable cp_data_a

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_data_a

Bins

NAME	COUNT	AT LEAST
all_ones	2	1
high	206	1
mid	430	1
low	229	1
zero	5	1

Summary for Variable cp_addr_a

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_addr_a

Bins

NAME	COUNT	AT LEAST
port_3	218	1
port_2	210	1
port_1	213	1
port_0	231	1

Summary for Variable cp_ready_a

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_ready_a

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
rejected	0	1	1

Covered bins

NAME	COUNT	AT LEAST
accepted	872	1

Summary for Cross cross_addr_data

Samples crossed: cp_addr_a cp_data_a

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	20	3	17	85.00	3

Automatically Generated Cross Bins for cross_addr_data

Uncovered bins

cp_addr_a	cp_data_a	COUNT	AT LEAST	NUMBER
[port_3]	[all_ones]	0	1	1
[port_3]	[zero]	0	1	1
[port_1]	[all_ones]	0	1	1

Covered bins

cp_addr_a	cp_data_a	COUNT	AT LEAST
port_3	low	54	1
port_3	mid	106	1
port_3	high	58	1
port_2	zero	1	1
port_2	low	61	1
port_2	mid	98	1
port_2	all_ones	1	1
port_2	high	49	1
port_1	zero	1	1
port_1	low	59	1
port_1	mid	111	1
port_1	high	42	1
port_0	zero	3	1
port_0	mid	115	1
port_0	low	55	1
port_0	all_ones	1	1
port_0	high	57	1

Summary for Cross cross_addr_ready

Samples crossed: cp_addr_a cp_ready_a

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	4	4	50.00	4

Automatically Generated Cross Bins for cross_addr_ready

Element holes

cp_addr_a	cp_ready_a	COUNT	AT LEAST	NUMBER
*	[rejected]	--	--	4

Covered bins

cp_addr_a	cp_ready_a	COUNT	AT LEAST
port_3	accepted	218	1
port_2	accepted	210	1
port_1	accepted	213	1
port_0	accepted	231	1

Summary for Variable cp_port_a_valid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_port_a_valid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST
valid	872	1

Summary for Variable cp_data_a

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_data_a

Bins

NAME	COUNT	AT LEAST
all_ones	2	1
high	206	1
mid	430	1
low	229	1
zero	5	1

Summary for Variable cp_addr_a

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_addr_a

Bins

NAME	COUNT	AT LEAST
port_3	218	1
port_2	210	1
port_1	213	1
port_0	231	1

Summary for Variable cp_ready_a

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_ready_a

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
rejected	0	1	1

Covered bins

NAME	COUNT	AT LEAST
accepted	872	1

Summary for Cross cross_addr_data

Samples crossed: cp_addr_a cp_data_a

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	20	3	17	85.00	3

Automatically Generated Cross Bins for cross_addr_data

Uncovered bins

cp_addr_a	cp_data_a	COUNT	AT LEAST	NUMBER
[port_3]	[all_ones]	0	1	1
[port_3]	[zero]	0	1	1
[port_1]	[all_ones]	0	1	1

Covered bins

cp_addr_a	cp_data_a	COUNT	AT LEAST
port_3	low	54	1
port_3	mid	106	1
port_3	high	58	1
port_2	zero	1	1
port_2	low	61	1
port_2	mid	98	1
port_2	all_ones	1	1
port_2	high	49	1
port_1	zero	1	1
port_1	low	59	1
port_1	mid	111	1
port_1	high	42	1
port_0	zero	3	1
port_0	mid	115	1
port_0	low	55	1
port_0	all_ones	1	1
port_0	high	57	1

Summary for Cross cross_addr_ready

Samples crossed: cp_addr_a cp_ready_a

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	4	4	50.00	4

Automatically Generated Cross Bins for cross_addr_ready

Element holes

cp_addr_a	cp_ready_a	COUNT	AT LEAST	NUMBER
*	[rejected]	--	--	4

Covered bins

cp_addr_a	cp_ready_a	COUNT	AT LEAST
port_3	accepted	218	1
port_2	accepted	210	1
port_1	accepted	213	1
port_0	accepted	231	1