Unified Coverage Report :: Group :: router_pkg::router_coverage::cg_output_transactions

Group : router_pkg::router_coverage::cg_output_transactions

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Group : router_pkg::router_coverage::cg_output_transactions

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.67	96.67	1	100	1	1	64	64

Source File(s) :
/scratch/cs199-buw/UVM_Practice/Router_UVM/env/router_coverage.svh

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb_top.me.obj.cg_output_transactions	96.67	1	100	1	64	64

Summary for Group router_pkg::router_coverage::cg_output_transactions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	20	2	18	90.00

Variables for Group router_pkg::router_coverage::cg_output_transactions

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_output_port	4	0	4	100.00	100	1	1	0
cp_output_data	5	0	5	100.00	100	1	1	0

Crosses for Group router_pkg::router_coverage::cg_output_transactions

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_port_data	20	2	18	90.00	100	1	1	0

Group Instance : tb_top.me.obj.cg_output_transactions

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.67	1	100	1	64	64

Summary for Group Instance tb_top.me.obj.cg_output_transactions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	20	2	18	90.00

Variables for Group Instance tb_top.me.obj.cg_output_transactions

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_output_port	4	0	4	100.00	100	1	1	0
cp_output_data	5	0	5	100.00	100	1	1	0

Crosses for Group Instance tb_top.me.obj.cg_output_transactions

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_port_data	20	2	18	90.00	100	1	1	0

Summary for Variable cp_output_port

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_output_port

Bins

NAME	COUNT	AT LEAST
port_3	425	1
port_2	424	1
port_1	455	1
port_0	440	1

Summary for Variable cp_output_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_output_data

Bins

NAME	COUNT	AT LEAST
all_ones	3	1
high	390	1
mid	882	1
low	460	1
zero	9	1

Summary for Cross cross_port_data

Samples crossed: cp_output_port cp_output_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	20	2	18	90.00	2

Automatically Generated Cross Bins for cross_port_data

Uncovered bins

cp_output_port	cp_output_data	COUNT	AT LEAST	NUMBER
[port_3]	[all_ones]	0	1	1
[port_1]	[all_ones]	0	1	1

Covered bins

cp_output_port	cp_output_data	COUNT	AT LEAST
port_3	zero	1	1
port_3	mid	210	1
port_3	low	112	1
port_3	high	102	1
port_2	zero	3	1
port_2	mid	212	1
port_2	low	124	1
port_2	all_ones	2	1
port_2	high	83	1
port_1	zero	2	1
port_1	low	115	1
port_1	mid	236	1
port_1	high	102	1
port_0	zero	3	1
port_0	mid	224	1
port_0	low	109	1
port_0	all_ones	1	1
port_0	high	103	1

Summary for Variable cp_output_port

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_output_port

Bins

NAME	COUNT	AT LEAST
port_3	425	1
port_2	424	1
port_1	455	1
port_0	440	1

Summary for Variable cp_output_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_output_data

Bins

NAME	COUNT	AT LEAST
all_ones	3	1
high	390	1
mid	882	1
low	460	1
zero	9	1

Summary for Cross cross_port_data

Samples crossed: cp_output_port cp_output_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	20	2	18	90.00	2

Automatically Generated Cross Bins for cross_port_data

Uncovered bins

cp_output_port	cp_output_data	COUNT	AT LEAST	NUMBER
[port_3]	[all_ones]	0	1	1
[port_1]	[all_ones]	0	1	1

Covered bins

cp_output_port	cp_output_data	COUNT	AT LEAST
port_3	zero	1	1
port_3	mid	210	1
port_3	low	112	1
port_3	high	102	1
port_2	zero	3	1
port_2	mid	212	1
port_2	low	124	1
port_2	all_ones	2	1
port_2	high	83	1
port_1	zero	2	1
port_1	low	115	1
port_1	mid	236	1
port_1	high	102	1
port_0	zero	3	1
port_0	mid	224	1
port_0	low	109	1
port_0	all_ones	1	1
port_0	high	103	1

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