Unified Coverage Report :: Group :: router_pkg::router_coverage::cg_port_b

Group : router_pkg::router_coverage::cg_port_b_transactions

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
71.67	71.67	1	100	1	1	64	64

Source File(s) :
/scratch/cs199-buw/UVM_Practice/Router_UVM/env/router_coverage.svh

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb_top.me.obj.cg_port_b_transactions	71.67	1	100	1	64	64

Summary for Group router_pkg::router_coverage::cg_port_b_transactions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	2	11	75.00
Crosses	28	8	20	65.00

Variables for Group router_pkg::router_coverage::cg_port_b_transactions

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_port_b_valid	2	1	1	50.00	100	1	1	0
cp_data_b	5	0	5	100.00	100	1	1	0
cp_addr_b	4	0	4	100.00	100	1	1	0
cp_ready_b	2	1	1	50.00	100	1	1	0

Crosses for Group router_pkg::router_coverage::cg_port_b_transactions

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_addr_data	20	4	16	80.00	100	1	1	0
cross_addr_ready	8	4	4	50.00	100	1	1	0

Group Instance : tb_top.me.obj.cg_port_b_transactions

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.67	1	100	1	64	64

Summary for Group Instance tb_top.me.obj.cg_port_b_transactions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	2	11	75.00
Crosses	28	8	20	65.00

Variables for Group Instance tb_top.me.obj.cg_port_b_transactions

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_port_b_valid	2	1	1	50.00	100	1	1	0
cp_data_b	5	0	5	100.00	100	1	1	0
cp_addr_b	4	0	4	100.00	100	1	1	0
cp_ready_b	2	1	1	50.00	100	1	1	0

Crosses for Group Instance tb_top.me.obj.cg_port_b_transactions

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_addr_data	20	4	16	80.00	100	1	1	0
cross_addr_ready	8	4	4	50.00	100	1	1	0

Summary for Variable cp_port_b_valid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_port_b_valid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST
valid	872	1

Summary for Variable cp_data_b

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_data_b

Bins

NAME	COUNT	AT LEAST
all_ones	1	1
high	184	1
mid	452	1
low	231	1
zero	4	1

Summary for Variable cp_addr_b

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_addr_b

Bins

NAME	COUNT	AT LEAST
port_3	207	1
port_2	214	1
port_1	242	1
port_0	209	1

Summary for Variable cp_ready_b

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_ready_b

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
rejected	0	1	1

Covered bins

NAME	COUNT	AT LEAST
accepted	872	1

Summary for Cross cross_addr_data

Samples crossed: cp_addr_b cp_data_b

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	20	4	16	80.00	4

Automatically Generated Cross Bins for cross_addr_data

Uncovered bins

cp_addr_b	cp_data_b	COUNT	AT LEAST	NUMBER
[port_3]	[all_ones]	0	1	1
[port_1]	[all_ones]	0	1	1
[port_0]	[all_ones]	0	1	1
[port_0]	[zero]	0	1	1

Covered bins

cp_addr_b	cp_data_b	COUNT	AT LEAST
port_3	zero	1	1
port_3	mid	104	1
port_3	low	58	1
port_3	high	44	1
port_2	zero	2	1
port_2	mid	114	1
port_2	low	63	1
port_2	all_ones	1	1
port_2	high	34	1
port_1	zero	1	1
port_1	low	56	1
port_1	mid	125	1
port_1	high	60	1
port_0	mid	109	1
port_0	low	54	1
port_0	high	46	1

Summary for Cross cross_addr_ready

Samples crossed: cp_addr_b cp_ready_b

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	4	4	50.00	4

Automatically Generated Cross Bins for cross_addr_ready

Element holes

cp_addr_b	cp_ready_b	COUNT	AT LEAST	NUMBER
*	[rejected]	--	--	4

Covered bins

cp_addr_b	cp_ready_b	COUNT	AT LEAST
port_3	accepted	207	1
port_2	accepted	214	1
port_1	accepted	242	1
port_0	accepted	209	1

Summary for Variable cp_port_b_valid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_port_b_valid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST
valid	872	1

Summary for Variable cp_data_b

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_data_b

Bins

NAME	COUNT	AT LEAST
all_ones	1	1
high	184	1
mid	452	1
low	231	1
zero	4	1

Summary for Variable cp_addr_b

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_addr_b

Bins

NAME	COUNT	AT LEAST
port_3	207	1
port_2	214	1
port_1	242	1
port_0	209	1

Summary for Variable cp_ready_b

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_ready_b

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
rejected	0	1	1

Covered bins

NAME	COUNT	AT LEAST
accepted	872	1

Summary for Cross cross_addr_data

Samples crossed: cp_addr_b cp_data_b

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	20	4	16	80.00	4

Automatically Generated Cross Bins for cross_addr_data

Uncovered bins

cp_addr_b	cp_data_b	COUNT	AT LEAST	NUMBER
[port_3]	[all_ones]	0	1	1
[port_1]	[all_ones]	0	1	1
[port_0]	[all_ones]	0	1	1
[port_0]	[zero]	0	1	1

Covered bins

cp_addr_b	cp_data_b	COUNT	AT LEAST
port_3	zero	1	1
port_3	mid	104	1
port_3	low	58	1
port_3	high	44	1
port_2	zero	2	1
port_2	mid	114	1
port_2	low	63	1
port_2	all_ones	1	1
port_2	high	34	1
port_1	zero	1	1
port_1	low	56	1
port_1	mid	125	1
port_1	high	60	1
port_0	mid	109	1
port_0	low	54	1
port_0	high	46	1

Summary for Cross cross_addr_ready

Samples crossed: cp_addr_b cp_ready_b

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	4	4	50.00	4

Automatically Generated Cross Bins for cross_addr_ready

Element holes

cp_addr_b	cp_ready_b	COUNT	AT LEAST	NUMBER
*	[rejected]	--	--	4

Covered bins

cp_addr_b	cp_ready_b	COUNT	AT LEAST
port_3	accepted	207	1
port_2	accepted	214	1
port_1	accepted	242	1
port_0	accepted	209	1