Line Coverage for Module : uvm_custom_install_verdi_recording
Toggle Coverage for Module : uvm_custom_install_verdi_recording
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| TOTAL | 412 | 21 | 5.10 | |
| ROUTINE | 104 | 1 | 0 | 0.00 |
| INITIAL | 125 | 84 | 21 | 25.00 |
| ROUTINE | 50 | 9 | 0 | 0.00 |
| ROUTINE | 67 | 9 | 0 | 0.00 |
| ROUTINE | 39 | 1 | 0 | 0.00 |
| ROUTINE | 40 | 1 | 0 | 0.00 |
| ROUTINE | 41 | 1 | 0 | 0.00 |
| ROUTINE | 43 | 1 | 0 | 0.00 |
| ROUTINE | 19 | 5 | 0 | 0.00 |
| ROUTINE | 34 | 8 | 0 | 0.00 |
| ROUTINE | 98 | 4 | 0 | 0.00 |
| ROUTINE | 110 | 14 | 0 | 0.00 |
| ROUTINE | 139 | 1 | 0 | 0.00 |
| ROUTINE | 147 | 1 | 0 | 0.00 |
| ROUTINE | 157 | 1 | 0 | 0.00 |
| ROUTINE | 173 | 1 | 0 | 0.00 |
| ROUTINE | 350 | 36 | 0 | 0.00 |
| ROUTINE | 433 | 67 | 0 | 0.00 |
| ROUTINE | 564 | 88 | 0 | 0.00 |
| ROUTINE | 723 | 31 | 0 | 0.00 |
| ROUTINE | 786 | 48 | 0 | 0.00 |
103 `ifdef VCS 104 0/1 ==> import "DPI-C" function string getenv(input string env_name); 105 `endif 106 `include "uvm_verdi_pli.svh" //Hide dumper tasks inside this module 107 static uvm_cmdline_processor clp; 108 string tr_args[$]; 109 uvm_coreservice_t cs; 110 uvm_verdi_tr_database verdi_db; 111 uvm_factory factory; 112 `ifndef UVM_VERDI_NO_FACTORY_RECORDING 113 uvm_verdi_factory verdi_factory; 114 `endif 115 process p; 116 string rand_state; 117 `ifdef VCS 118 string env_str,vc_env_str="",sanity_file_name=""; 119 int file_handle=0, is_sanity_exist=0, is_vpd_record = 0; 120 string env_vcs_home = "", env_vcs_uvm_home =""; 121 int is_vcs_home_exist = 0, is_vcs_uvm_home_exist = 0; 122 `endif 123 124 initial begin 125 1/1 p = process::self(); 126 1/1 if (p != null) 127 1/1 rand_state = p.get_randstate(); ==> MISSING_ELSE 128 1/1 verdi_clp = verdi_cmdline_processor::get_inst(); 129 1/1 clp = uvm_cmdline_processor::get_inst(); 130 1/1 pli_inst = uvm_verdi_pli::get_inst(); 131 1/1 cs = uvm_coreservice_t::get(); 132 `ifdef VCS 133 1/1 env_vcs_home = getenv("VCS_HOME"); 134 1/1 if (env_vcs_home!="") 135 1/1 is_vcs_home_exist = 1; ==> MISSING_ELSE 136 1/1 env_vcs_uvm_home = getenv("VCS_UVM_HOME"); 137 1/1 if (env_vcs_uvm_home!="") 138 0/1 ==> is_vcs_uvm_home_exist = 1; MISSING_ELSE 139 1/1 if (clp.get_arg_matches("+UVM_VPD_RECORD", tr_args)) 140 0/1 ==> is_vpd_record = 1; MISSING_ELSE 141 1/1 env_str = getenv("SNPS_SIM_DEFAULT_GUI"); 142 1/1 vc_env_str = getenv("VC_HOME"); 143 1/1 if (vc_env_str!="")begin 144 0/1 ==> sanity_file_name = {vc_env_str,"/etc/.sanity"}; 145 0/1 ==> file_handle = $fopen(sanity_file_name,"r"); 146 0/1 ==> if (file_handle!=0) begin 147 0/1 ==> if (is_vpd_record) 148 0/1 ==> is_sanity_exist = 0; 149 else 150 0/1 ==> is_sanity_exist = 1; 151 0/1 ==> $fclose(file_handle); 152 end ==> MISSING_ELSE 153 end MISSING_ELSE 154 `endif 155 156 `ifndef UVM_NO_VERDI_RECORD 157 1/1 if (verdi_clp.is_verdi_trace_ral()) begin 158 uvm_root r_obj; 159 // 9001338477 160 string verb_settings[$]; 161 string verb_string; 162 int verb_count; 163 // 164 165 // 9001338477 166 0/1 ==> verb_count = clp.get_arg_values("+UVM_VERBOSITY=",verb_settings); 167 0/1 ==> if (verb_count > 0) begin 168 0/1 ==> verb_string = verb_settings[0]; 169 0/1 ==> case(verb_string) 170 0/1 ==> "UVM_NONE" : user_verbosity = UVM_NONE; 171 0/1 ==> "NONE" : user_verbosity = UVM_NONE; 172 0/1 ==> "UVM_LOW" : user_verbosity = UVM_LOW; 173 0/1 ==> "LOW" : user_verbosity = UVM_LOW; 174 0/1 ==> "UVM_MEDIUM" : user_verbosity = UVM_MEDIUM; 175 0/1 ==> "MEDIUM" : user_verbosity = UVM_MEDIUM; 176 0/1 ==> "UVM_HIGH" : user_verbosity = UVM_HIGH; 177 0/1 ==> "HIGH" : user_verbosity = UVM_HIGH; 178 0/1 ==> "UVM_FULL" : user_verbosity = UVM_FULL; 179 0/1 ==> "FULL" : user_verbosity = UVM_FULL; 180 0/1 ==> "UVM_DEBUG" : user_verbosity = UVM_DEBUG; 181 0/1 ==> "DEBUG" : user_verbosity = UVM_DEBUG; 182 default : begin 183 0/1 ==> user_verbosity = verb_string.atoi(); 184 0/1 ==> if(user_verbosity > 0) 185 0/1 ==> uvm_report_info("NSTVERB", $sformatf("Non-standard verbosity value, using provided '%0d'.", user_verbosity), UVM_NONE); ==> MISSING_ELSE 186 0/1 ==> if(user_verbosity == 0) begin 187 0/1 ==> user_verbosity = UVM_MEDIUM; 188 0/1 ==> uvm_report_warning("ILLVERB", "Illegal verbosity value, using default of UVM_MEDIUM.", UVM_NONE); 189 end ==> MISSING_ELSE 190 end 191 endcase 192 end ==> MISSING_ELSE 193 // 194 0/1 ==> r_obj = uvm_root::get(); 195 0/1 ==> r_obj.set_report_id_verbosity("RegModel", UVM_HIGH); 196 0/1 ==> r_obj.set_report_id_verbosity("uvm_reg_map", UVM_FULL); 197 end MISSING_ELSE 198 `endif 199 200 // Register the verdi_catcher to dump messages into FSDB 201 `ifdef VCS 202 1/1 if ((clp.get_arg_matches("+UVM_LOG_RECORD", tr_args)&& (!clp.get_arg_matches("+UVM_VPD_RECORD", tr_args))) 203 ||(clp.get_arg_matches("+UVM_LOG_RECORD", tr_args)&&(env_str=="verdi")) 204 ||verdi_clp.is_verdi_trace_fac()||verdi_clp.is_verdi_trace_msg()||verdi_clp.is_verdi_trace_uvm_aware() 205 ||verdi_clp.is_verdi_trace_ral()||verdi_clp.is_verdi_trace_dht() 206 ||(clp.get_arg_matches("+UVM_LOG_RECORD", tr_args) && verdi_clp.is_minus_gui_verdi()) 207 ||(clp.get_arg_matches("+UVM_LOG_RECORD", tr_args)&&is_sanity_exist) 208 ||verdi_clp.is_verdi_trace_ralwave()||verdi_clp.is_verdi_trace_compwave()) 209 begin 210 `else 211 if ((clp.get_arg_matches("+UVM_LOG_RECORD", tr_args)&& (!clp.get_arg_matches("+UVM_VPD_RECORD", tr_args))) 212 ||verdi_clp.is_verdi_trace_fac()||verdi_clp.is_verdi_trace_msg() 213 ||verdi_clp.is_verdi_trace_uvm_aware()||verdi_clp.is_verdi_trace_ral() 214 ||verdi_clp.is_verdi_trace_dht()) 215 begin 216 `endif 217 static verdi_report_catcher _verdi_catcher; 218 219 0/1 ==> _verdi_catcher = new(); 220 0/1 ==> uvm_report_cb::add(null,_verdi_catcher); 221 0/1 ==> if (verdi_clp.is_verdi_trace_compwave()||verdi_clp.is_verdi_trace_dht() 222 ||verdi_clp.is_verdi_trace_uvm_aware()||verdi_clp.is_verdi_trace_ral()) begin 223 uvm_dhier_component dhier_comp; 224 225 0/1 ==> dhier_comp = new("DHIER_COMP", uvm_root::get()); 226 end ==> MISSING_ELSE 227 `ifdef VCS 228 // 9001375412 Allow user to set dumping level 229 0/1 ==> if (verdi_clp.is_verdi_trace_ralwave()) begin 230 static string val_str=""; 231 232 0/1 ==> void'(verdi_clp.get_arg_value("+UVM_OBJ_DUMP_LEVEL=", val_str)); 233 0/1 ==> if (is_vcs_uvm_home_exist) 234 0/1 ==> pli_inst.dump_class_object_by_file("${VCS_UVM_HOME}/verdi/register.config",val_str); 235 0/1 ==> else if (is_vcs_home_exist) 236 0/1 ==> pli_inst.dump_class_object_by_file("${VCS_HOME}/etc/uvm-1.2/verdi/register.config",val_str); ==> MISSING_ELSE 237 end ==> MISSING_ELSE 238 // 239 // 9001375412 Allow user to set dumping level 240 0/1 ==> if (verdi_clp.is_verdi_trace_compwave()) begin 241 static string val_str=""; 242 243 0/1 ==> void'(verdi_clp.get_arg_value("+UVM_OBJ_DUMP_LEVEL=", val_str)); 244 0/1 ==> if (is_vcs_uvm_home_exist) 245 0/1 ==> pli_inst.dump_comp_object_by_file("${VCS_UVM_HOME}/verdi/component.config",val_str); 246 0/1 ==> else if (is_vcs_home_exist) 247 0/1 ==> pli_inst.dump_comp_object_by_file("${VCS_HOME}/etc/uvm-1.2/verdi/component.config",val_str); ==> MISSING_ELSE 248 end ==> MISSING_ELSE 249 // 250 `endif 251 0/1 ==> if (verdi_clp.is_verdi_trace_uvm_aware()||verdi_clp.is_verdi_trace_fac()) begin 252 0/1 ==> factory = cs.get_factory(); 253 `ifndef UVM_VERDI_NO_FACTORY_RECORDING 254 // create new factory 255 0/1 ==> verdi_factory = new(); 256 // set the delegate 257 0/1 ==> verdi_factory.delegate=factory; 258 // enable new factory 259 0/1 ==> cs.set_factory(verdi_factory); 260 `endif 261 end ==> MISSING_ELSE 262 end MISSING_ELSE 263 264 // Register the uvm_verdi_recorder to record transactions into FSDB 265 `ifdef VCS 266 1/1 if ((clp.get_arg_matches("+UVM_TR_RECORD", tr_args)&& (!clp.get_arg_matches("+UVM_VPD_RECORD", tr_args))) 267 ||(clp.get_arg_matches("+UVM_TR_RECORD", tr_args)&&(env_str=="verdi")) 268 ||verdi_clp.is_verdi_trace_tlm() 269 ||(clp.get_arg_matches("+UVM_TR_RECORD", tr_args)&&verdi_clp.is_minus_gui_verdi()) 270 ||(clp.get_arg_matches("+UVM_TR_RECORD", tr_args)&&is_sanity_exist)) 271 begin 272 `else 273 if ((clp.get_arg_matches("+UVM_TR_RECORD", tr_args)&& (!clp.get_arg_matches("+UVM_VPD_RECORD", tr_args))) 274 ||verdi_clp.is_verdi_trace_tlm()) 275 begin 276 `endif 277 0/1 ==> verdi_db = new(); 278 0/1 ==> cs.set_default_tr_database(verdi_db); 279 0/1 ==> if (clp.get_arg_matches("+UVM_DISABLE_AUTO_COMPONENT", tr_args)) begin280 0/2 ==> `uvm_info("VERDI_TR_AUTO", "+UVM_DISABLE_AUTO_COMPONENT enabled but transaction recording enabled, usage model requires user to explicitly set recording_detail on components", UVM_MEDIUM)
uvm_info("VERDI_TR_AUTO", "+UVM_DISABLE_AUTO_COMPONENT enabled but transaction recording enabled, usage model requires user to explicitly set recording_detail on components", UVM_MEDIUM): 280.1 `ifdef ZEMI4UVM 280.2 (* zemi4_uvm_attribute=1 *) 280.3 `endif 280.4 begin 280.5 0/1 ==> if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"VERDI_TR_AUTO")) 280.6 0/1 ==> uvm_report_info ("VERDI_TR_AUTO", "+UVM_DISABLE_AUTO_COMPONENT enabled but transaction recording enabled, usage model requires user to explicitly set recording_detail on components", UVM_MEDIUM, "/share/instsww/synopsys-new/vcs/T-2022.06-SP2-9//etc/uvm-1.2/verdi/uvm_custom_install_verdi_recorder.sv", 280, "", 1); 280.7 end ==> MISSING_ELSE 281 end 282 else begin
uvm_info("VERDI_TR_AUTO", "+UVM_TR_RECORD implicitly enables recording_details to UVM_FULL for all components. For explicit control use +UVM_DISABLE_AUTO_COMPONENT and set recording_detail on components accordingly", UVM_MEDIUM): 283.1 `ifdef ZEMI4UVM 283.2 (* zemi4_uvm_attribute=1 *) 283.3 `endif 283.4 begin 283.5 0/1 ==> if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"VERDI_TR_AUTO")) 283.6 0/1 ==> uvm_report_info ("VERDI_TR_AUTO", "+UVM_TR_RECORD implicitly enables recording_details to UVM_FULL for all components. For explicit control use +UVM_DISABLE_AUTO_COMPONENT and set recording_detail on components accordingly", UVM_MEDIUM, "/share/instsww/synopsys-new/vcs/T-2022.06-SP2-9//etc/uvm-1.2/verdi/uvm_custom_install_verdi_recorder.sv", 283, "", 1); 283.7 end ==> MISSING_ELSE 284 0/1 ==> uvm_config_db#(uvm_bitstream_t)::set(uvm_root::get(), "*", "recording_detail", UVM_FULL); 285 end 286 end MISSING_ELSE 287 1/1 if (p != null) 288 1/1 p.set_randstate(rand_state); ==> MISSING_ELSE
FILE: /share/instsww/synopsys-new/vcs/T-2022.06-SP2-9//etc/uvm-1.2/verdi/uvm_verdi_tr_database.svh 50 0/1 ==> if (!plusargs_tested) begin 51 0/1 ==> if (verdi_clp.is_verdi_trace_tlm()) begin 52 0/1 ==> enable_port_recording = 1; 53 0/1 ==> if (verdi_clp.is_verdi_trace_imp()) 54 0/1 ==> enable_imp_port_recording = 1 ; ==> MISSING_ELSE 55 end ==> MISSING_ELSE 56 0/1 ==> if (clp.get_arg_matches("+verdi_recorder_debug",trace_args)) 57 0/1 ==> enable_verdi_debug = 1; ==> MISSING_ELSE 58 0/1 ==> plusargs_tested = 1; 59 end ==> MISSING_ELSE 60 0/1 ==> return plusargs_tested; 61 endfunction 62 63 function bit test_tlm2_port_plusargs (); 64 static verdi_cmdline_processor verdi_clp = verdi_cmdline_processor::get_inst(); 65 static uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst(); 66 string trace_args[$]; 67 0/1 ==> if (!plusargs_tested) begin 68 0/1 ==> if (verdi_clp.is_verdi_trace_tlm2()) begin 69 0/1 ==> enable_tlm2_port_recording = 1; 70 0/1 ==> if (verdi_clp.is_verdi_trace_imp()) 71 0/1 ==> enable_imp_port_recording = 1 ; ==> MISSING_ELSE 72 end ==> MISSING_ELSE 73 0/1 ==> if (clp.get_arg_matches("+verdi_recorder_debug",trace_args)) 74 0/1 ==> enable_verdi_debug = 1; ==> MISSING_ELSE 75 0/1 ==> plusargs_tested = 1; 76 end ==> MISSING_ELSE 77 0/1 ==> return plusargs_tested;
FILE: /share/instsww/synopsys-new/vcs/T-2022.06-SP2-9//etc/uvm-1.2/verdi/./dpi/uvm_verdi_dpi.svh 39 0/1 ==> import "DPI-C" context function void retrieve_reg_def_class(input string var_name, input int _handle, input int is_objid_only=0); 40 0/1 ==> import "DPI-C" context function string retrieve_def_class(input string var_name, output int objid); 41 0/1 ==> import "DPI-C" context function int record_reg_decl_name(input int handle, input string parent_var_name, input string var_name, input string obj_name); 42 import "DPI-C" context function int check_is_sequencer(); 43 0/1 ==> import "DPI-C" context function string remove_array_index(input string name_w_ary_idx, output chandle name_c_ptr);
FILE: /share/instsww/synopsys-new/vcs/T-2022.06-SP2-9//etc/uvm-1.2/verdi/uvm_verdi_reg_recording.sv 19 0/1 ==> new_reg_name = remove_array_index(reg_name, _ptr); 20 21 0/1 ==> if(g_visited_regname.exists(parent_handle) && 22 g_visited_regname[parent_handle].exists(new_reg_name)) 23 0/1 ==> return; ==> MISSING_ELSE 24 25 0/1 ==> g_visited_regname[parent_handle][new_reg_name] = 1'b1; 26 27 0/1 ==> g_refclass_id[class_name][new_reg_name] = id; 28 endfunction 29 30 function automatic int find_refclass_id(input uvm_object parent_handle, input string class_name, input string reg_name); 31 string _reg_name_wo_range; 32 chandle _ptr; 33 34 0/1 ==> _reg_name_wo_range = remove_array_index(reg_name, _ptr); 35 36 0/1 ==> if(g_visited_regname.exists(parent_handle) && 37 g_visited_regname[parent_handle].exists(_reg_name_wo_range)) begin 38 39 0/1 ==> if(g_refclass_id.exists(class_name) && 40 g_refclass_id[class_name].exists(_reg_name_wo_range)) 41 0/1 ==> g_refclass_id[class_name].delete(_reg_name_wo_range); ==> MISSING_ELSE 42 43 0/1 ==> return 0; 44 end ==> MISSING_ELSE 45 46 47 0/1 ==> if(g_refclass_id.exists(class_name) && g_refclass_id[class_name].exists(_reg_name_wo_range)) begin 48 0/1 ==> return g_refclass_id[class_name][_reg_name_wo_range]; 49 end ==> MISSING_ELSE 50 51 0/1 ==> return 0; 52 endfunction 53 54 function automatic uvm_reg_map_info retrieve_mem_map_info(uvm_reg_map _map, uvm_mem _mem); 55 uvm_reg_map _parent_map; 56 uvm_reg_map_info _map_info; 57 58 _map_info = null; 59 _parent_map = _map.get_parent_map(); 60 61 while(_parent_map!= null) begin 62 _map = _parent_map; 63 _map_info = _map.get_mem_map_info(_mem, 0); 64 65 if(_map_info) 66 return _map_info; 67 68 _parent_map = _map.get_parent_map(); 69 end 70 71 return null; 72 endfunction 73 74 function automatic uvm_reg_map_info retrieve_reg_map_info(uvm_reg_map _map, uvm_reg _reg); 75 uvm_reg_map _parent_map; 76 uvm_reg_map_info _map_info; 77 78 _map_info = null; 79 _parent_map = _map.get_parent_map(); 80 81 while(_parent_map!= null) begin 82 _map = _parent_map; 83 _map_info = _map.get_reg_map_info(_reg, 0); 84 85 if(_map_info) 86 return _map_info; 87 88 _parent_map = _map.get_parent_map(); 89 end 90 91 return null; 92 endfunction 93 94 95 function automatic bit has_blk_hdl_path(uvm_reg_block _blk); 96 uvm_reg_block _parent_blk; 97 98 0/1 ==> _parent_blk = _blk.get_parent(); 99 100 0/1 ==> if(_parent_blk == null) 101 0/1 ==> return _blk.has_hdl_path(); 102 else 103 0/1 ==> return has_blk_hdl_path(_parent_blk) & _blk.has_hdl_path(); 104 endfunction 105 106 function int pli_reghier_begin_event(input string streamN); 107 string comp_stream, des_str; 108 longint unsigned streamId, handle; 109 110 0/1 ==> streamId = 0; 111 0/1 ==> handle = 0; 112 0/1 ==> $sformat(comp_stream, "UVM.REG_HIER.%0s", streamN); 113 114 0/1 ==> if (!streamArrByName.exists(comp_stream)) begin 115 // 9001353389 116 `ifdef VERDI_REPLACE_DPI_WITH_PLI 117 des_str = "+description+type=register"; 118 `else 119 0/1 ==> des_str = "type=register"; 120 `endif 121 0/1 ==> streamId = pli_inst.create_stream_begin(comp_stream,des_str); 122 0/1 ==> streamArrByName[comp_stream] = streamId; 123 0/1 ==> pli_inst.create_stream_end(streamId); 124 end else begin 125 0/1 ==> streamId = streamArrByName[comp_stream]; 126 end 127 128 0/1 ==> handle = pli_inst.begin_tr(streamId,"+type+message"); 129 130 0/1 ==> if (handle==0) begin 131 0/1 ==> $display("Failed to create transaction!\n"); 132 0/1 ==> return 0; 133 end ==> MISSING_ELSE 134 135 0/1 ==> return handle; 136 endfunction 137 138 function void pli_reghier_set_label(input int handle, input string label); 139 0/1 ==> pli_inst.set_label(handle, label); 140 endfunction 141 142 function void pli_reghier_add_attribute_string(input int handle, input string attrName, input string valName); 143 // 6000025017 144 `ifdef VERDI_REPLACE_DPI_WITH_PLI 145 pli_inst.add_attribute_string(handle, $sformatf("%0s", valName), $sformatf("+name+%0s", attrName), "+numbit+0"); 146 `else 147 0/1 ==> pli_inst.add_attribute_string(handle, $sformatf("%0s", valName), $sformatf("%0s", attrName), ""); 148 `endif 149 // 150 endfunction 151 152 function void pli_reghier_add_attribute_int(input int handle, input string attr_name, input int attr_value); 153 // 6000025017 154 `ifdef VERDI_REPLACE_DPI_WITH_PLI 155 pli_inst.add_attribute_int(handle, attr_value, $sformatf("+name+%0s", attr_name)); 156 `else 157 0/1 ==> pli_inst.add_attribute_int(handle, attr_value, $sformatf("%0s", attr_name)); 158 `endif 159 // 160 endfunction 161 162 function void pli_reghier_add_attribute_logic(input int handle, input string attr_name, input logic [1023:0] attr_value, input string radix, input integer numbits=1024); 163 // 6000025017 164 `ifdef VERDI_REPLACE_DPI_WITH_PLI 165 pli_inst.add_attribute_logic(handle, attr_value, $sformatf("+name+%0s", attr_name), radix, $sformatf("+numbit+%0d", numbits)); 166 `else 167 pli_inst.add_attribute_logic(handle, attr_value, $sformatf("%0s", attr_name), radix, $sformatf("%0d", numbits)); 168 `endif 169 // 170 endfunction 171 172 function void pli_reghier_end_event(input int handle); 173 0/1 ==> pli_inst.end_tr(handle); 174 175 endfunction 176 177 function automatic void record_reghier_map(uvm_reg_map _map); begin 178 uvm_reg _regs[$], _reg; 179 uvm_reg_field _fields[$], _field; 180 uvm_mem _mems[$], _mem; 181 int _handle; 182 string _full_name, _address, _regid, _label_name; 183 uvm_sequencer_base _sequencer; 184 uvm_reg_map _parent_map; 185 uvm_reg_block _parent_blk; 186 uvm_reg_addr_t _base_addr; 187 int _decl; 188 bit _need_end_event; 189 int g_policy_id[string]; 190 191 _need_end_event = 1'b0; 192 _decl = 0; 193 _full_name = _map.get_full_name(); 194 _handle = pli_reghier_begin_event(_full_name); 195 196 _parent_map = _map.get_parent_map(); 197 _parent_blk = _map.get_parent(); 198 199 if(_parent_blk) 200 $sformat(_label_name, "MAP_%0d_%0d", _map.get_inst_id(), _parent_blk.get_inst_id()); 201 else 202 $sformat(_label_name, "MAP_%0d_", _map.get_inst_id()); 203 204 pli_reghier_set_label(_handle, _label_name); 205 206 pli_reghier_add_attribute_string(_handle, "name", _full_name); 207 if(_parent_blk) begin 208 if (!verdi_clp.is_verdi_trace_no_decl()) 209 _decl = record_reg_decl_name(_handle, "_parent_blk", "_map", _map.get_name()); 210 end 211 212 if(_parent_map) begin 213 pli_reghier_add_attribute_int(_handle, "parent_map_id", _parent_map.get_inst_id()); 214 end 215 216 retrieve_reg_def_class("_map", _handle); 217 218 pli_reghier_add_attribute_int(_handle, "bus_width_in_bytes", _map.get_n_bytes()); 219 220 _base_addr = _map.get_base_addr(); 221 pli_reghier_add_attribute_logic(_handle, "base_address", _base_addr, "+radix+hex", $size(_base_addr)); 222 223 _sequencer = _map.get_sequencer(); 224 225 if(_sequencer !=null) 226 pli_reghier_add_attribute_string(_handle, "sequencer", _sequencer.get_full_name()); 227 228 pli_reghier_end_event(_handle); 229 230 _map.get_registers(_regs, UVM_NO_HIER); 231 232 _need_end_event = 1'b0; 233 if(_regs.size()>0) begin 234 _need_end_event = 1'b1; 235 _handle = pli_reghier_begin_event(_full_name); 236 pli_reghier_set_label(_handle, _label_name); 237 //pli_reghier_add_attribute_int(_handle, "inst_id", _map.get_inst_id()); 238 end 239 240 while(_regs.size() > 0) begin 241 uvm_reg_addr_t _addr, _offset; 242 uvm_reg_map_info _map_info; 243 string _right; 244 uvm_map_access_recorder _inst; 245 246 _reg = _regs.pop_front(); 247 248 if(_map) 249 _map_info = _map.get_reg_map_info(_reg, 0); 250 251 if(_map_info==null) 252 _map_info = retrieve_reg_map_info(_map, _reg); 253 254 if(_map_info!=null && !_map_info.unmapped) begin 255 256 _right = _reg.get_rights(_map); 257 258 if(!g_policy_id.exists(_right)) begin 259 int _policy_size; 260 261 _policy_size = g_policy_id.size(); 262 pli_reghier_add_attribute_string(_handle, $sformatf("policy_%0d", (_policy_size+1)), _right); 263 g_policy_id[_right] = _policy_size+1; 264 end 265 pli_reghier_add_attribute_int(_handle, $sformatf("reg_%0d_access_policy_id", _reg.get_inst_id()), g_policy_id[_right]); 266 267 _addr = _reg.get_address(_map); 268 _inst = uvm_map_access_recorder::get_inst(); 269 _inst.insert_register(_addr, _map.get_full_name(), _reg); 270 271 pli_reghier_add_attribute_logic(_handle, $sformatf("reg_%0d_address", _reg.get_inst_id()), _addr, "+radix+hex", $size(_addr)); 272 273 _offset = _reg.get_offset(_map); 274 pli_reghier_add_attribute_logic(_handle, $sformatf("reg_%0d_offset", _reg.get_inst_id()), _offset, "+radix+hex", $size(_offset)); 275 276 _reg.get_fields(_fields); 277 while(_fields.size() > 0) begin 278 279 _field = _fields.pop_front(); 280 _right = _field.get_access(_map); 281 282 if(!g_policy_id.exists(_right)) begin 283 int _policy_size; 284 285 _policy_size = g_policy_id.size(); 286 pli_reghier_add_attribute_string(_handle, $sformatf("policy_%0d", (_policy_size+1)), _right); 287 g_policy_id[_right] = _policy_size+1; 288 end 289 pli_reghier_add_attribute_int(_handle, $sformatf("field_%0d_access_policy_id", _field.get_inst_id()), g_policy_id[_right]); 290 291 end 292 end 293 end 294 295 if(_need_end_event==1'b1) 296 pli_reghier_end_event(_handle); 297 298 _map.get_memories(_mems, UVM_NO_HIER); 299 _need_end_event =1'b0; 300 if(_mems.size() > 0) begin 301 _need_end_event =1'b1; 302 _handle = pli_reghier_begin_event(_full_name); 303 pli_reghier_set_label(_handle, _label_name); 304 //pli_reghier_add_attribute_int(_handle, "inst_id", _map.get_inst_id()); 305 end 306 307 while(_mems.size() > 0) begin 308 uvm_reg_addr_t _addr, _offset; 309 uvm_reg_map_info _map_info; 310 uvm_map_access_recorder _inst; 311 312 _mem = _mems.pop_front(); 313 314 if(_map) 315 _map_info = _map.get_mem_map_info(_mem, 0); 316 317 if(_map_info==null) 318 _map_info = retrieve_mem_map_info(_map, _mem); 319 320 if(_map_info!=null && !_map_info.unmapped) begin 321 $sformat(_regid, "mem_%0d_access_policy", _mem.get_inst_id()); 322 pli_reghier_add_attribute_string(_handle, _regid, _mem.get_access(_map)); 323 324 _addr = _mem.get_address(0, _map); // base address 325 _inst = uvm_map_access_recorder::get_inst(); 326 _inst.insert_register(_addr, _map.get_full_name(), _mem); 327 328 $sformat(_regid, "mem_%0d_address", _mem.get_inst_id()); 329 pli_reghier_add_attribute_logic(_handle, _regid, _addr, "+radix+hex", $size(_addr)); 330 331 332 _offset = _mem.get_offset(0, _map); // base offset 333 $sformat(_regid, "mem_%0d_offset", _mem.get_inst_id()); 334 pli_reghier_add_attribute_logic(_handle, _regid, _offset, "+radix+hex", $size(_offset)); 335 end 336 end 337 338 if(_need_end_event==1'b1) 339 pli_reghier_end_event(_handle); 340 341 end 342 endfunction 343 344 function automatic void record_reghier_field(uvm_reg_field _field, string _stream_name, int refId); begin 345 int _handle, _objid; 346 uvm_reg _parent_reg; 347 uvm_reg_block _parent_blk; 348 uvm_reg_file _parent_regfile; 349 350 0/1 ==> int _decl, _classRefId=0; 351 string _field_class_name; 352 uvm_reg_field _cur_field; 353 static verdi_cmdline_processor verdi_clp = verdi_cmdline_processor::get_inst(); 354 static int g_fieldclass_bit_lsb[string][int][int]; 355 356 0/1 ==> _handle = pli_reghier_begin_event(_stream_name); 357 358 0/1 ==> _parent_reg = _field.get_parent(); 359 360 0/1 ==> _decl = 0; 361 0/1 ==> if(refId!=0) begin 362 0/1 ==> _decl= 1; 363 end ==> MISSING_ELSE 364 365 0/1 ==> if((_parent_reg!=null) && refId==0) begin 366 0/1 ==> if (!verdi_clp.is_verdi_trace_no_decl()) 367 0/1 ==> _decl = record_reg_decl_name(_handle, "_parent_reg", "_field", _field.get_name()); ==> MISSING_ELSE 368 end ==> MISSING_ELSE 369 370 0/1 ==> if(_parent_reg) 371 0/1 ==> pli_reghier_set_label(_handle, $sformatf("FIELD_%0d_%0d", _field.get_inst_id(), _parent_reg.get_inst_id())); 372 else 373 0/1 ==> pli_reghier_set_label(_handle, $sformatf("FIELD_%0d_", _field.get_inst_id())); 374 375 0/1 ==> _cur_field = _field; 376 0/1 ==> _field_class_name = retrieve_def_class("_cur_field", _objid); 377 378 0/1 ==> if(_field_class_name.len()>0 && 379 g_fieldclass_bit_lsb.exists(_field_class_name) && 380 g_fieldclass_bit_lsb[_field_class_name].exists(_field.get_n_bits()) && 381 g_fieldclass_bit_lsb[_field_class_name][_field.get_n_bits()].exists(_field.get_lsb_pos())) begin 382 383 0/1 ==> _classRefId = g_fieldclass_bit_lsb[_field_class_name][_field.get_n_bits()][_field.get_lsb_pos()]; 384 385 end else begin 386 0/1 ==> g_fieldclass_bit_lsb[_field_class_name][_field.get_n_bits()][_field.get_lsb_pos()] = _field.get_inst_id(); 387 end 388 389 0/1 ==> if(refId!=0 && refId!=_classRefId) 390 0/1 ==> pli_reghier_add_attribute_int(_handle, "reference_declaration_inst_id", refId); ==> MISSING_ELSE 391 0/1 ==> if(_classRefId!=0 && _classRefId!=refId) 392 0/1 ==> pli_reghier_add_attribute_int(_handle, "reference_class_inst_id", _classRefId); ==> MISSING_ELSE 393 0/1 ==> if(refId!=0 && refId==_classRefId) 394 0/1 ==> pli_reghier_add_attribute_int(_handle, "reference_class_declaration_inst_id", _classRefId); ==> MISSING_ELSE 395 396 397 0/1 ==> if(_classRefId==0) begin 398 0/1 ==> pli_reghier_add_attribute_int(_handle, "num_bits", _field.get_n_bits()); 399 0/1 ==> pli_reghier_add_attribute_int(_handle, "lsb_pos", _field.get_lsb_pos()); 400 end ==> MISSING_ELSE 401 402 0/1 ==> pli_reghier_add_attribute_string(_handle, "name", $sformatf("%s.%s.%s", _stream_name, _parent_reg.get_name(), _field.get_name())); 403 404 0/1 ==> if(_decl==0 && _parent_reg!=null) begin 405 0/1 ==> _parent_blk = _parent_reg.get_parent(); 406 0/1 ==> if (!verdi_clp.is_verdi_trace_no_decl()) 407 0/1 ==> _decl = record_reg_decl_name(_handle, "_parent_blk", "_field", _field.get_name()); ==> MISSING_ELSE 408 end ==> MISSING_ELSE 409 410 0/1 ==> if(_classRefId==0) 411 0/1 ==> retrieve_reg_def_class("_field", _handle); 412 `ifdef VCS 413 0/1 ==> else if(_objid!=0) 414 0/1 ==> pli_reghier_add_attribute_string(_handle, "snps_object_id", $sformatf("\\%s @%0d", _field_class_name, _objid)); ==> MISSING_ELSE 415 `endif 416 417 0/1 ==> pli_reghier_end_event(_handle); 418 419 end 420 endfunction 421 422 function automatic string record_reghier_regfile(uvm_reg_file _regfile); begin 423 uvm_reg_block _top_blk; 424 uvm_reg_file _parent_regfile; 425 int _handle, _num_hdl; 426 string _full_name; 427 string _hdl_paths[$], _hdl, _hdl_attr, _blk_class_name, _regfile_class_name, _cur_regfile_class_name; 428 int _decl, _refId, _objid; 429 uvm_reg_file _cur_regfile; 430 static verdi_cmdline_processor verdi_clp = verdi_cmdline_processor::get_inst(); 431 static int g_regfile_class[string]; 432 433 0/1 ==> _decl = 0; 434 0/1 ==> _num_hdl = 0; 435 0/1 ==> _regfile_class_name = ""; 436 437 0/1 ==> if(g_visited_regfile.exists(_regfile)) begin 438 0/1 ==> return g_visited_regfile[_regfile]; 439 end ==> MISSING_ELSE 440 441 0/1 ==> _parent_regfile = _regfile.get_regfile(); 442 0/1 ==> _top_blk = _regfile.get_parent(); 443 444 445 0/1 ==> _refId = 0; 446 0/1 ==> if(_parent_regfile!=null && g_regfile_handle_class_name.exists(_parent_regfile)) begin 447 0/1 ==> _regfile_class_name = g_regfile_handle_class_name[_parent_regfile]; 448 end ==> MISSING_ELSE 449 450 0/1 ==> if(_parent_regfile!=null && _regfile_class_name.len()==0) begin 451 0/1 ==> _regfile_class_name = retrieve_def_class("_parent_regfile", _objid); 452 0/1 ==> if(_regfile_class_name.len() > 0) 453 0/1 ==> g_regfile_handle_class_name[_parent_regfile] = _regfile_class_name; ==> MISSING_ELSE 454 end ==> MISSING_ELSE 455 456 0/1 ==> if(_regfile_class_name.len() > 0) 457 0/1 ==> _refId = find_refclass_id(uvm_object'(_parent_regfile), _regfile_class_name, _regfile.get_name()); ==> MISSING_ELSE 458 459 0/1 ==> _blk_class_name = ""; 460 0/1 ==> if(_refId==0) begin 461 0/1 ==> _blk_class_name = retrieve_def_class("_top_blk", _objid); 462 0/1 ==> _refId = find_refclass_id(uvm_object'(_top_blk), _blk_class_name, _regfile.get_name()); 463 end ==> MISSING_ELSE 464 465 0/1 ==> if(_parent_regfile) begin 466 467 0/1 ==> _full_name = record_reghier_regfile(_parent_regfile); 468 0/1 ==> _full_name = {_full_name, ".", _regfile.get_name()}; 469 470 0/1 ==> g_visited_regfile[_regfile] = _full_name; 471 0/1 ==> _handle = pli_reghier_begin_event(_full_name); 472 473 0/1 ==> if (!verdi_clp.is_verdi_trace_no_decl() && _refId==0) begin 474 0/1 ==> _decl = record_reg_decl_name(_handle, "_parent_regfile", "_regfile", _regfile.get_name()); 475 0/1 ==> if(_decl) 476 0/1 ==> insert_refclass_id(uvm_object'(_parent_regfile), _regfile_class_name, _regfile.get_name(), _regfile.get_inst_id()); ==> MISSING_ELSE 477 478 0/1 ==> if(_decl==0 && _top_blk!=null) begin 479 0/1 ==> _decl = record_reg_decl_name(_handle, "_top_blk", "_regfile", _regfile.get_name()); 480 0/1 ==> if(_decl) 481 0/1 ==> insert_refclass_id(uvm_object'(_top_blk), _blk_class_name, _regfile.get_name(), _regfile.get_inst_id()); ==> MISSING_ELSE 482 end ==> MISSING_ELSE 483 484 end ==> MISSING_ELSE 485 end else begin 486 0/1 ==> _full_name = _regfile.get_full_name(); 487 0/1 ==> g_visited_regfile[_regfile] = _full_name; 488 0/1 ==> _handle = pli_reghier_begin_event(_full_name); 489 490 0/1 ==> if(_top_blk) begin 491 0/1 ==> if (!verdi_clp.is_verdi_trace_no_decl() && _refId==0) begin 492 0/1 ==> _decl = record_reg_decl_name(_handle, "_top_blk", "_regfile", _regfile.get_name()); 493 0/1 ==> if(_decl) 494 0/1 ==> insert_refclass_id(uvm_object'(_top_blk), _blk_class_name, _regfile.get_name(), _regfile.get_inst_id()); ==> MISSING_ELSE 495 end ==> MISSING_ELSE 496 end ==> MISSING_ELSE 497 end 498 499 0/1 ==> if(_parent_regfile) begin 500 0/1 ==> pli_reghier_set_label(_handle, $sformatf("REGFILE_%0d_%0d", _regfile.get_inst_id(), _parent_regfile.get_inst_id())); 501 0/1 ==> end else if(_top_blk) begin 502 0/1 ==> pli_reghier_set_label(_handle, $sformatf("REGFILE_%0d_%0d", _regfile.get_inst_id(), _top_blk.get_inst_id())); 503 end else begin 504 0/1 ==> pli_reghier_set_label(_handle, $sformatf("REGFILE_%0d_", _regfile.get_inst_id())); 505 end 506 507 0/1 ==> pli_reghier_add_attribute_string(_handle, "name", _full_name); 508 509 0/1 ==> _objid = 0; 510 0/1 ==> if(_refId!=0) begin 511 0/1 ==> pli_reghier_add_attribute_int(_handle, "reference_class_declaration_inst_id", _refId); 512 0/1 ==> retrieve_reg_def_class("_regfile", _handle, 1); 513 end else begin 514 515 0/1 ==> _cur_regfile = _regfile; 516 0/1 ==> _cur_regfile_class_name = retrieve_def_class("_cur_regfile", _objid); 517 518 0/1 ==> if(_cur_regfile_class_name.len()>0 && g_regfile_class.exists(_cur_regfile_class_name)) begin 519 520 0/1 ==> pli_reghier_add_attribute_int(_handle, "reference_class_inst_id", g_regfile_class[_cur_regfile_class_name]); 521 0/1 ==> pli_reghier_add_attribute_string(_handle, "snps_object_id", $sformatf("\\%s @%0d", _cur_regfile_class_name, _objid)); 522 523 end else begin 524 525 0/1 ==> g_regfile_class[_cur_regfile_class_name] = _regfile.get_inst_id(); 526 0/1 ==> retrieve_reg_def_class("_regfile", _handle); 527 528 end 529 end 530 531 0/1 ==> if (_regfile.has_hdl_path()) 532 0/1 ==> _regfile.get_hdl_path(_hdl_paths); ==> MISSING_ELSE 533 534 0/1 ==> while(_hdl_paths.size() > 0 ) begin 535 0/1 ==> _hdl = _hdl_paths.pop_front(); 536 0/1 ==> if(_hdl.len()>0) begin 537 0/1 ==> $sformat(_hdl_attr, "hdl_path_%0d", _num_hdl++); 538 0/1 ==> pli_reghier_add_attribute_string(_handle, _hdl_attr, _hdl); 539 end ==> MISSING_ELSE 540 end ==> WHILE_FALSE 541 0/1 ==> pli_reghier_end_event(_handle); 542 543 0/1 ==> return _full_name; 544 end 545 endfunction 546 547 function automatic void record_reghier_reg(uvm_reg _reg); begin 548 uvm_reg _cur_reg; 549 uvm_reg_file _parent_regfile; 550 uvm_reg_block _parent_blk; 551 string _stream_name, _reg_name, _label_name, _class_name; 552 uvm_reg_field _fields[$], _field; 553 uvm_reg_map _default_map; 554 555 uvm_hdl_path_concat _hdl_paths[$], _hdl_path; 556 uvm_hdl_path_slice _hdl_slice; 557 string _hdl, _hdl_attr_name, _reg_class_name, _blk_class_name, _regfile_class_name; 558 int _hdl_offset, _hdl_size, _hdl_idx, _slice_idx; 559 int _handle, _inst_id; 560 int _decl, _refId, _classRefId, _objid; 561 static verdi_cmdline_processor verdi_clp = verdi_cmdline_processor::get_inst(); 562 static int g_regclass_bits[string][int]; 563 564 0/1 ==> _hdl_idx = 0; 565 0/1 ==> _slice_idx = 0; 566 0/1 ==> _decl = 0; 567 0/1 ==> _regfile_class_name = ""; 568 0/1 ==> _blk_class_name = ""; 569 570 // Handle regfiles 571 0/1 ==> _parent_regfile = _reg.get_regfile(); 572 0/1 ==> _parent_blk = _reg.get_parent(); 573 574 0/1 ==> _refId = 0; 575 0/1 ==> _inst_id = _reg.get_inst_id(); 576 577 0/1 ==> if(_parent_regfile!=null && g_regfile_handle_class_name.exists(_parent_regfile)) begin 578 0/1 ==> _regfile_class_name = g_regfile_handle_class_name[_parent_regfile]; 579 end ==> MISSING_ELSE 580 581 0/1 ==> if(_parent_regfile!=null && _regfile_class_name.len()==0) begin 582 0/1 ==> _regfile_class_name = retrieve_def_class("_parent_regfile", _objid); 583 0/1 ==> g_regfile_handle_class_name[_parent_regfile] = _regfile_class_name; 584 end ==> MISSING_ELSE 585 586 0/1 ==> if(_regfile_class_name.len() > 0) 587 0/1 ==> _refId = find_refclass_id(uvm_object'(_parent_regfile), _regfile_class_name, _reg.get_name()); ==> MISSING_ELSE 588 589 0/1 ==> if(_refId==0 && (_parent_blk!=null)) begin 590 0/1 ==> if(g_regblk_handle_class_name.exists(_parent_blk)) begin 591 0/1 ==> _blk_class_name = g_regblk_handle_class_name[_parent_blk]; 592 end else begin 593 0/1 ==> _blk_class_name = retrieve_def_class("_parent_blk", _objid); 594 0/1 ==> g_regblk_handle_class_name[_parent_blk] = _blk_class_name; 595 end 596 0/1 ==> _refId = find_refclass_id(uvm_object'(_parent_blk), _blk_class_name, _reg.get_name()); 597 end ==> MISSING_ELSE 598 599 0/1 ==> if(_parent_regfile) begin 600 601 0/1 ==> _stream_name = record_reghier_regfile(_parent_regfile); 602 0/1 ==> _handle = pli_reghier_begin_event(_stream_name); 603 604 0/1 ==> if (!verdi_clp.is_verdi_trace_no_decl() && _refId==0) begin 605 0/1 ==> _decl = record_reg_decl_name(_handle, "_parent_regfile", "_reg", _reg.get_name()); 606 0/1 ==> if(_decl) 607 0/1 ==> insert_refclass_id(uvm_object'(_parent_regfile), _regfile_class_name, _reg.get_name(), _inst_id); ==> MISSING_ELSE 608 end ==> MISSING_ELSE 609 610 end else begin 611 0/1 ==> _stream_name = _parent_blk.get_full_name(); 612 0/1 ==> _handle = pli_reghier_begin_event(_stream_name); 613 end 614 615 616 0/1 ==> if(_parent_blk!=null && _decl==0 && _refId==0) begin 617 0/1 ==> if (!verdi_clp.is_verdi_trace_no_decl()) begin 618 0/1 ==> _decl = record_reg_decl_name(_handle, "_parent_blk", "_reg", _reg.get_name()); 619 0/1 ==> if(_decl) 620 0/1 ==> insert_refclass_id(uvm_object'(_parent_blk), _blk_class_name, _reg.get_name(), _inst_id); ==> MISSING_ELSE 621 end ==> MISSING_ELSE 622 end ==> MISSING_ELSE 623 624 0/1 ==> _cur_reg = _reg; 625 0/1 ==> _reg_class_name = retrieve_def_class("_cur_reg", _objid); 626 627 0/1 ==> _classRefId = 0; 628 0/1 ==> if(_reg_class_name.len()>0 && g_regclass_bits.exists(_reg_class_name) && g_regclass_bits[_reg_class_name].exists(_reg.get_n_bits())) begin 629 0/1 ==> _classRefId = g_regclass_bits[_reg_class_name][_reg.get_n_bits()]; 630 end else begin 631 0/1 ==> g_regclass_bits[_reg_class_name][_reg.get_n_bits()] = _inst_id; 632 end 633 634 0/1 ==> if(_refId!=0 && _classRefId!=_refId) 635 0/1 ==> pli_reghier_add_attribute_int(_handle, "reference_declaration_inst_id", _refId); ==> MISSING_ELSE 636 0/1 ==> if(_classRefId!=0 && _classRefId!=_refId) 637 0/1 ==> pli_reghier_add_attribute_int(_handle, "reference_class_inst_id", _classRefId); ==> MISSING_ELSE 638 0/1 ==> if(_refId!=0 && _classRefId==_refId) 639 0/1 ==> pli_reghier_add_attribute_int(_handle, "reference_class_declaration_inst_id", _classRefId); ==> MISSING_ELSE 640 641 0/1 ==> _default_map = _reg.get_default_map(); 642 643 0/1 ==> if(_parent_regfile!=null && _default_map!=null) begin 644 0/1 ==> $sformat(_label_name, "REG_%0d_%0d_%0d", _inst_id, _parent_regfile.get_inst_id(), _default_map.get_inst_id()); 645 0/1 ==> end else if(_parent_blk) begin 646 0/1 ==> if (_default_map) 647 0/1 ==> $sformat(_label_name, "REG_%0d_%0d_%0d", _inst_id, _parent_blk.get_inst_id(), _default_map.get_inst_id()); 648 else 649 0/1 ==> $sformat(_label_name, "REG_%0d_%0d", _inst_id, _parent_blk.get_inst_id()); 650 end else begin 651 0/1 ==> if (_default_map) 652 0/1 ==> $sformat(_label_name, "REG_%0d__%0d", _inst_id, _default_map.get_inst_id()); 653 else 654 0/1 ==> $sformat(_label_name, "REG_%0d", _inst_id); 655 end 656 657 0/1 ==> pli_reghier_set_label(_handle, _label_name); 658 659 0/1 ==> if(_classRefId==0) 660 0/1 ==> pli_reghier_add_attribute_int(_handle, "num_bits", _reg.get_n_bits()); ==> MISSING_ELSE 661 662 0/1 ==> $sformat(_reg_name, "%s.%s", _stream_name, _reg.get_name()); 663 0/1 ==> pli_reghier_add_attribute_string(_handle, "name", _reg_name); 664 665 666 0/1 ==> if(_classRefId==0) 667 0/1 ==> retrieve_reg_def_class("_reg", _handle); 668 `ifdef VCS 669 0/1 ==> else if(_objid!=0) 670 0/1 ==> pli_reghier_add_attribute_string(_handle, "snps_object_id", $sformatf("\\%s @%0d", _reg_class_name, _objid)); ==> MISSING_ELSE 671 `endif 672 673 0/1 ==> if (_reg.has_hdl_path()) 674 0/1 ==> _reg.get_hdl_path(_hdl_paths); ==> MISSING_ELSE 675 676 0/1 ==> while(_hdl_paths.size() > 0) begin 677 0/1 ==> _hdl_path = _hdl_paths.pop_front(); 678 0/1 ==> for(_slice_idx=0; _slice_idx < _hdl_path.slices.size(); _slice_idx++) begin 679 0/1 ==> $sformat(_hdl_attr_name, "hdl_slice_path_%0d_%0d", _hdl_idx, _slice_idx); 680 0/1 ==> pli_reghier_add_attribute_string(_handle, _hdl_attr_name, _hdl_path.slices[_slice_idx].path); 681 0/1 ==> $sformat(_hdl_attr_name, "hdl_slice_offset_%0d_%0d", _hdl_idx, _slice_idx); 682 0/1 ==> pli_reghier_add_attribute_int(_handle, _hdl_attr_name, _hdl_path.slices[_slice_idx].offset); 683 0/1 ==> $sformat(_hdl_attr_name, "hdl_slice_size_%0d_%0d", _hdl_idx, _slice_idx); 684 0/1 ==> pli_reghier_add_attribute_int(_handle, _hdl_attr_name, _hdl_path.slices[_slice_idx].size); 685 end 686 0/1 ==> _hdl_idx++; 687 end ==> WHILE_FALSE 688 689 0/1 ==> pli_reghier_end_event(_handle); 690 691 692 // Iterate reg fields 693 0/1 ==> _refId = 0; 694 695 0/1 ==> _reg.get_fields(_fields); 696 697 0/1 ==> while(_fields.size() > 0) begin 698 0/1 ==> _field = _fields.pop_front(); 699 700 0/1 ==> _refId = find_refclass_id(uvm_object'(_reg), _reg_class_name, _field.get_name()); 701 0/1 ==> if(_refId==0) 702 0/1 ==> insert_refclass_id(uvm_object'(_reg), _reg_class_name, _field.get_name(), _field.get_inst_id()); ==> MISSING_ELSE 703 0/1 ==> record_reghier_field(_field, _stream_name, _refId); 704 end 705 706 707 end 708 endfunction 709 710 function automatic void record_reghier_mem(uvm_mem _mem); begin 711 string _mem_name, _blk_name; 712 int _handle; 713 uvm_reg_block _parent_blk; 714 uvm_reg_map _default_map; 715 716 uvm_hdl_path_concat _hdl_paths[$], _hdl_path; 717 uvm_hdl_path_slice _hdl_slice; 718 string _hdl, _hdl_attr_name; 719 int _hdl_offset, _hdl_size, _hdl_idx, _slice_idx; 720 int _decl; 721 static verdi_cmdline_processor verdi_clp = verdi_cmdline_processor::get_inst(); 722 723 0/1 ==> _hdl_idx = 0; 724 0/1 ==> _slice_idx = 0; 725 0/1 ==> _mem_name = _mem.get_full_name(); 726 0/1 ==> _parent_blk = _mem.get_parent(); 727 0/1 ==> _blk_name = _parent_blk.get_full_name(); 728 0/1 ==> _decl = 0; 729 730 0/1 ==> _handle = pli_reghier_begin_event(_mem_name); 731 732 0/1 ==> if (!verdi_clp.is_verdi_trace_no_decl()) 733 0/1 ==> _decl = record_reg_decl_name(_handle, "_parent_blk", "_mem", _mem.get_name()); ==> MISSING_ELSE 734 735 0/1 ==> _default_map = _mem.get_default_map(); 736 737 0/1 ==> if(_parent_blk!=null && _default_map!=null) begin 738 0/1 ==> pli_reghier_set_label(_handle, $sformatf("MEM_%0d_%0d_%0d", _mem.get_inst_id(), _parent_blk.get_inst_id(), _default_map.get_inst_id())); 739 0/1 ==> end else if(_default_map) begin 740 0/1 ==> pli_reghier_set_label(_handle, $sformatf("MEM_%0d__%0d", _mem.get_inst_id(), _default_map.get_inst_id())); 741 end ==> MISSING_ELSE 742 743 0/1 ==> pli_reghier_add_attribute_string(_handle, "name", _mem_name); 744 0/1 ==> pli_reghier_add_attribute_int(_handle, "width_in_bits", _mem.get_n_bits()); 745 0/1 ==> pli_reghier_add_attribute_int(_handle, "memory_size", _mem.get_size()); 746 747 0/1 ==> retrieve_reg_def_class("_mem", _handle); 748 749 750 0/1 ==> if (_mem.has_hdl_path()) 751 0/1 ==> _mem.get_hdl_path(_hdl_paths); ==> MISSING_ELSE 752 753 0/1 ==> while(_hdl_paths.size() > 0) begin 754 0/1 ==> _hdl_path = _hdl_paths.pop_front(); 755 0/1 ==> for(_slice_idx=0; _slice_idx < _hdl_path.slices.size(); _slice_idx++) begin 756 0/1 ==> $sformat(_hdl_attr_name, "hdl_slice_path_%0d_%0d", _hdl_idx, _slice_idx); 757 0/1 ==> pli_reghier_add_attribute_string(_handle, _hdl_attr_name, _hdl_path.slices[_slice_idx].path); 758 0/1 ==> $sformat(_hdl_attr_name, "hdl_slice_offset_%0d_%0d", _hdl_idx, _slice_idx); 759 0/1 ==> pli_reghier_add_attribute_int(_handle, _hdl_attr_name, _hdl_path.slices[_slice_idx].offset); 760 0/1 ==> $sformat(_hdl_attr_name, "hdl_slice_size_%0d_%0d", _hdl_idx, _slice_idx); 761 0/1 ==> pli_reghier_add_attribute_int(_handle, _hdl_attr_name, _hdl_path.slices[_slice_idx].size); 762 end 763 0/1 ==> _hdl_idx++; 764 end ==> WHILE_FALSE 765 766 0/1 ==> pli_reghier_end_event(_handle); 767 768 end 769 endfunction 770 771 function automatic void record_reghier_blk(uvm_reg_block _blk); begin 772 uvm_reg _regs[$], _reg; 773 //uvm_reg_map _maps[$], _map; 774 uvm_reg_block _blks[$], _parent_blk, _sub_blk; 775 uvm_mem _mems[$], _mem; 776 int _handle, _num_hdl; 777 string _hdl_path, _block_name; 778 uvm_reg_map _default_map; 779 string _hdl_paths[$], _hdl, _hdl_attr; 780 int _decl; 781 static int max_reg_dump_limit = 5000; 782 static int max_reg_dump_limit_check = 0; 783 static int dumped_reg_num=0; 784 static int is_limit_message_recorded=0; 785 786 0/1 ==> _num_hdl = 0; 787 0/1 ==> _decl = 0; 788 789 // Record Block Attributes 790 0/1 ==> _block_name = _blk.get_full_name(); 791 0/1 ==> _handle = pli_reghier_begin_event(_block_name); 792 793 0/1 ==> _default_map = _blk.get_default_map(); 794 795 0/1 ==> _parent_blk = _blk.get_parent(); 796 0/1 ==> if(_parent_blk!=null && _default_map!=null) begin 797 0/1 ==> pli_reghier_set_label(_handle, $sformatf("BLOCK_%0d_%0d_%0d", _blk.get_inst_id(), _parent_blk.get_inst_id(), _default_map.get_inst_id())); 798 0/1 ==> end else if(_default_map) begin 799 0/1 ==> pli_reghier_set_label(_handle, $sformatf("BLOCK_%0d__%0d", _blk.get_inst_id(), _default_map.get_inst_id())); 800 end ==> MISSING_ELSE 801 802 0/1 ==> pli_reghier_add_attribute_string(_handle, "name", _block_name); 803 804 0/1 ==> _parent_blk = _blk.get_parent(); 805 0/1 ==> if(_parent_blk) begin 806 807 0/1 ==> if (!verdi_clp.is_verdi_trace_no_decl()) 808 0/1 ==> _decl = record_reg_decl_name(_handle, "_parent_blk", "_blk", _blk.get_name()); ==> MISSING_ELSE 809 810 end ==> MISSING_ELSE 811 812 813 0/1 ==> retrieve_reg_def_class("_blk", _handle); 814 815 816 0/1 ==> if (_blk.is_hdl_path_root() || has_blk_hdl_path(_blk)) 817 0/1 ==> _blk.get_full_hdl_path(_hdl_paths); ==> MISSING_ELSE 818 0/1 ==> while(_hdl_paths.size() > 0 ) begin 819 0/1 ==> _hdl = _hdl_paths.pop_front(); 820 0/1 ==> if(_hdl.len()>0) begin 821 0/1 ==> $sformat(_hdl_attr, "hdl_path_%0d", _num_hdl++); 822 0/1 ==> pli_reghier_add_attribute_string(_handle, _hdl_attr, _hdl); 823 end ==> MISSING_ELSE 824 end ==> WHILE_FALSE 825 826 0/1 ==> pli_reghier_end_event(_handle); 827 828 0/1 ==> _hdl_path = ""; 829 830 // Iterate registers 831 0/1 ==> if(max_reg_dump_limit_check==0) begin 832 uvm_cmdline_processor clp; 833 string val_str; 834 835 0/1 ==> val_str = ""; 836 0/1 ==> max_reg_dump_limit_check = 1; 837 0/1 ==> clp = uvm_cmdline_processor::get_inst(); 838 0/1 ==> if (clp.get_arg_value("+UVM_REG_DUMP_LIMIT=", val_str)) 839 0/1 ==> max_reg_dump_limit = val_str.atoi(); ==> MISSING_ELSE 840 841 end ==> MISSING_ELSE 842 843 0/1 ==> if(verdi_clp.is_verdi_trace_ral() && (dumped_reg_num < max_reg_dump_limit||max_reg_dump_limit==0)) 844 0/1 ==> _blk.get_registers(_regs, UVM_NO_HIER); ==> MISSING_ELSE 845 846 847 0/1 ==> while(_regs.size() > 0) begin 848 0/1 ==> int _refId=0; 849 850 0/1 ==> _reg = _regs.pop_front(); 851 852 0/1 ==> if(verdi_clp.is_verdi_trace_ral() && (dumped_reg_num < max_reg_dump_limit||max_reg_dump_limit==0)) begin 853 0/1 ==> record_reghier_reg(_reg); 854 0/1 ==> dumped_reg_num++; 855 0/1 ==> end else if(is_limit_message_recorded==0) begin 856 0/1 ==> _handle = pli_reghier_begin_event("max_reg_recorded"); 857 0/1 ==> is_limit_message_recorded = 1; 858 0/1 ==> pli_reghier_set_label(_handle, $sformatf("MAX_%0d_REG_RECORDED", max_reg_dump_limit)); 859 0/1 ==> pli_reghier_end_event(_handle); 860 861 end ==> MISSING_ELSE 862 end ==> WHILE_FALSE 863 864 0/1 ==> _blk.get_memories(_mems, UVM_NO_HIER); 865 0/1 ==> while(_mems.size() > 0) begin 866 0/1 ==> _mem = _mems.pop_front(); 867 0/1 ==> record_reghier_mem(_mem);
Toggle Coverage for Module : uvm_custom_install_verdi_recording
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 6 | 0 | 0.00 |
| Total Bits | 12 | 0 | 0.00 |
| Total Bits 0->1 | 6 | 0 | 0.00 |
| Total Bits 1->0 | 6 | 0 | 0.00 |
| Signals | 6 | 0 | 0.00 |
| Signal Bits | 12 | 0 | 0.00 |
| Signal Bits 0->1 | 6 | 0 | 0.00 |
| Signal Bits 1->0 | 6 | 0 | 0.00 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| hooks_version_flag | No | No | No |
| plusargs_tested | No | No | No |
| enable_verdi_debug | No | No | No |
| enable_port_recording | No | No | No |
| enable_tlm2_port_recording | No | No | No |
| enable_imp_port_recording | No | No | No |