Line Coverage for Module :
dual_port_router
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 34 | 34 | 100.00 |
| ALWAYS | 38 | 5 | 5 | 100.00 |
| ALWAYS | 50 | 14 | 14 | 100.00 |
| ALWAYS | 71 | 15 | 15 | 100.00 |
37 always_ff @(posedge clk or negedge rst_n) begin
38 1/1 if (!rst_n) begin
39 1/1 ctrl_reg <= 32'h1; // Default: Enabled, Port A priority
40 1/1 end else if (reg_en && reg_we) begin
41 2/2 if (reg_addr == 4'h0) ctrl_reg <= reg_wdata;
==> MISSING_ELSE
42 end
MISSING_ELSE
43 end
44 assign reg_rdata = (reg_addr == 4'h0) ? ctrl_reg :
45 (reg_addr == 4'h8) ? collision_cnt : 32'h0;
46
47 // --- Arbitration Logic (For Virtual Sequencer practice) ---
48 logic use_a;
49 always_comb begin
50 1/1 ready_a = 1'b0;
51 1/1 ready_b = 1'b0;
52 1/1 use_a = 1'b0;
53
54 1/1 if (ctrl_reg[0]) begin // If Global Enable is set
55 1/1 if (valid_a && valid_b) begin
56 1/1 use_a = !ctrl_reg[1]; // Use priority bit to decide
57 1/1 ready_a = use_a;
58 1/1 ready_b = !use_a;
59 1/1 end else if (valid_a) begin
60 1/1 use_a = 1'b1;
61 1/1 ready_a = 1'b1;
62 1/1 end else if (valid_b) begin
63 1/1 use_a = 1'b0;
64 1/1 ready_b = 1'b1;
65 end
MISSING_ELSE
66 end
MISSING_ELSE
67 end
68
69 // --- Data Path ---
70 always_ff @(posedge clk or negedge rst_n) begin
71 1/1 if (!rst_n) begin
72 1/1 for (int i=0; i<4; i++) begin
73 1/1 data_out[i] <= 8'h0;
74 1/1 valid_out[i] <= 1'b0;
75 end
76 1/1 collision_cnt <= 32'h0;
77 end else begin
78 // Default: clear valid bits
79 2/2 for (int i=0; i<4; i++) valid_out[i] <= 1'b0;
80
81 // Increment collision counter if both try to send
82 2/2 if (valid_a && valid_b) collision_cnt <= collision_cnt + 1;
MISSING_ELSE
83
84 1/1 if (use_a) begin
85 1/1 data_out[addr_a] <= data_a;
86 1/1 valid_out[addr_a] <= 1'b1;
87 1/1 end else if (ready_b) begin
88 1/1 data_out[addr_b] <= data_b;
89 1/1 valid_out[addr_b] <= 1'b1;
90 end
MISSING_ELSE
Cond Coverage for Module :
dual_port_router
| Total | Covered | Percent |
|---|
| Conditions | 13 | 11 | 84.62 |
| Logical | 13 | 11 | 84.62 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 40
EXPRESSION (reg_en && reg_we)
---1-- ---2--
| -1- | -2- | Status |
|---|
| 0 | 1 | Not Covered |
| 1 | 0 | Covered |
| 1 | 1 | Covered |
LINE 44
EXPRESSION ((reg_addr == 4'b0) ? ctrl_reg : ((reg_addr == 4'h8) ? collision_cnt : 32'b0))
---------1--------
| -1- | Status |
|---|
| 0 | Covered |
| 1 | Covered |
LINE 44
SUB-EXPRESSION ((reg_addr == 4'h8) ? collision_cnt : 32'b0)
---------1--------
| -1- | Status |
|---|
| 0 | Not Covered |
| 1 | Covered |
LINE 55
EXPRESSION (valid_a && valid_b)
---1--- ---2---
| -1- | -2- | Status |
|---|
| 0 | 1 | Covered |
| 1 | 0 | Covered |
| 1 | 1 | Covered |
LINE 82
EXPRESSION (valid_a && valid_b)
---1--- ---2---
| -1- | -2- | Status |
|---|
| 0 | 1 | Covered |
| 1 | 0 | Covered |
| 1 | 1 | Covered |
Toggle Coverage for Module :
dual_port_router
| Total | Covered | Percent |
| Totals |
18 |
12 |
66.67 |
| Total Bits |
322 |
118 |
36.65 |
| Total Bits 0->1 |
161 |
60 |
37.27 |
| Total Bits 1->0 |
161 |
58 |
36.02 |
| | | |
| Ports |
15 |
11 |
73.33 |
| Port Bits |
192 |
97 |
50.52 |
| Port Bits 0->1 |
96 |
49 |
51.04 |
| Port Bits 1->0 |
96 |
48 |
50.00 |
| | | |
| Signals |
3 |
1 |
33.33 |
| Signal Bits |
130 |
21 |
16.15 |
| Signal Bits 0->1 |
65 |
11 |
16.92 |
| Signal Bits 1->0 |
65 |
10 |
15.38 |
Port Details
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| clk |
Yes |
Yes |
Yes |
INPUT |
| rst_n |
No |
No |
Yes |
INPUT |
| reg_addr[2:0] |
No |
No |
No |
INPUT |
| reg_addr[3] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[1:0] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[3:2] |
No |
No |
No |
INPUT |
| reg_wdata[4] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[5] |
No |
No |
No |
INPUT |
| reg_wdata[9:6] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[10] |
No |
No |
No |
INPUT |
| reg_wdata[11] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[12] |
No |
No |
No |
INPUT |
| reg_wdata[14:13] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[16:15] |
No |
No |
No |
INPUT |
| reg_wdata[17] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[18] |
No |
No |
No |
INPUT |
| reg_wdata[19] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[20] |
No |
No |
No |
INPUT |
| reg_wdata[21] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[23:22] |
No |
No |
No |
INPUT |
| reg_wdata[24] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[25] |
No |
No |
No |
INPUT |
| reg_wdata[26] |
Yes |
Yes |
Yes |
INPUT |
| reg_wdata[30:27] |
No |
No |
No |
INPUT |
| reg_wdata[31] |
Yes |
Yes |
Yes |
INPUT |
| reg_en |
Yes |
Yes |
Yes |
INPUT |
| reg_we |
Yes |
Yes |
Yes |
INPUT |
| reg_rdata[2:0] |
Yes |
Yes |
Yes |
OUTPUT |
| reg_rdata[6:3] |
No |
No |
No |
OUTPUT |
| reg_rdata[7] |
Yes |
Yes |
Yes |
OUTPUT |
| reg_rdata[31:8] |
No |
No |
No |
OUTPUT |
| data_a[7:0] |
Yes |
Yes |
Yes |
INPUT |
| addr_a[1:0] |
Yes |
Yes |
Yes |
INPUT |
| valid_a |
Yes |
Yes |
Yes |
INPUT |
| ready_a |
Yes |
Yes |
Yes |
OUTPUT |
| data_b[7:0] |
Yes |
Yes |
Yes |
INPUT |
| addr_b[1:0] |
Yes |
Yes |
Yes |
INPUT |
| valid_b |
Yes |
Yes |
Yes |
INPUT |
| ready_b |
Yes |
Yes |
Yes |
OUTPUT |
Signal Details
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| ctrl_reg[1:0] |
Yes |
Yes |
Yes |
| ctrl_reg[31:2] |
No |
No |
No |
| collision_cnt[6:0] |
Yes |
Yes |
Yes |
| collision_cnt[7] |
No |
No |
Yes |
| collision_cnt[31:8] |
No |
No |
No |
| use_a |
Yes |
Yes |
Yes |