Line Coverage for Module :
tb_top
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| INITIAL | 15 | 4 | 4 | 100.00 |
| INITIAL | 20 | 5 | 5 | 100.00 |
| INITIAL | 59 | 6 | 6 | 100.00 |
14 initial begin
15 1/1 clk = 0;
16 3/3 forever #5 clk = ~clk;
17 end
18
19 initial begin
20 1/1 rst_n = 0;
21 3/3 repeat(5) @(posedge clk);
REPEAT_FALSE
22 1/1 rst_n = 1;
23 end
24
25
26 dual_port_router_if vif (clk, rst_n);
27
28 dual_port_router dut (
29 .clk (clk),
30 .rst_n (rst_n),
31
32 //ctrl regs
33 .reg_addr (vif.reg_addr),
34 .reg_wdata (vif.reg_wdata),
35 .reg_en (vif.reg_en),
36 .reg_we (vif.reg_we),
37 .reg_rdata (vif.reg_rdata),
38
39 //Port A signals
40 .data_a (vif.data_a),
41 .addr_a (vif.addr_a),
42 .valid_a (vif.valid_a),
43 .ready_a (vif.ready_a),
44
45 //Port B Signals
46 .data_b (vif.data_b),
47 .addr_b (vif.addr_b),
48 .valid_b (vif.valid_b),
49 .ready_b (vif.ready_b),
50
51 //output signals
52 .data_out (vif.data_out),
53 .valid_out (vif.valid_out)
54
55 );
56
57
58 initial begin
59 1/1 uvm_config_db#(virtual dual_port_router_if)::set(null, "*", "vif", vif);
60
61 // VCD for GTKWave
62 1/1 $dumpfile("dump.vcd");
63 1/1 $dumpvars(0, tb_top);
64
65 // VPD for DVE
66 1/1 $vcdplusfile("vcdplus.vpd");
67 1/1 $vcdpluson(0, tb_top);
68
69 1/1 run_test();
Toggle Coverage for Module :
tb_top
| Total | Covered | Percent |
| Totals |
2 |
1 |
50.00 |
| Total Bits |
4 |
3 |
75.00 |
| Total Bits 0->1 |
2 |
2 |
100.00 |
| Total Bits 1->0 |
2 |
1 |
50.00 |
| | | |
| Signals |
2 |
1 |
50.00 |
| Signal Bits |
4 |
3 |
75.00 |
| Signal Bits 0->1 |
2 |
2 |
100.00 |
| Signal Bits 1->0 |
2 |
1 |
50.00 |
Signal Details
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| clk |
Yes |
Yes |
Yes |
| rst_n |
No |
No |
Yes |