Toggle Coverage for Module :
dual_port_router_if
| Total | Covered | Percent |
| Totals |
15 |
11 |
73.33 |
| Total Bits |
192 |
97 |
50.52 |
| Total Bits 0->1 |
96 |
49 |
51.04 |
| Total Bits 1->0 |
96 |
48 |
50.00 |
| | | |
| Ports |
2 |
1 |
50.00 |
| Port Bits |
4 |
3 |
75.00 |
| Port Bits 0->1 |
2 |
2 |
100.00 |
| Port Bits 1->0 |
2 |
1 |
50.00 |
| | | |
| Signals |
13 |
10 |
76.92 |
| Signal Bits |
188 |
94 |
50.00 |
| Signal Bits 0->1 |
94 |
47 |
50.00 |
| Signal Bits 1->0 |
94 |
47 |
50.00 |
Port Details
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| clk |
Yes |
Yes |
Yes |
INPUT |
| rst_n |
No |
No |
Yes |
INPUT |
Signal Details
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| reg_addr[2:0] |
No |
No |
No |
| reg_addr[3] |
Yes |
Yes |
Yes |
| reg_wdata[1:0] |
Yes |
Yes |
Yes |
| reg_wdata[3:2] |
No |
No |
No |
| reg_wdata[4] |
Yes |
Yes |
Yes |
| reg_wdata[5] |
No |
No |
No |
| reg_wdata[9:6] |
Yes |
Yes |
Yes |
| reg_wdata[10] |
No |
No |
No |
| reg_wdata[11] |
Yes |
Yes |
Yes |
| reg_wdata[12] |
No |
No |
No |
| reg_wdata[14:13] |
Yes |
Yes |
Yes |
| reg_wdata[16:15] |
No |
No |
No |
| reg_wdata[17] |
Yes |
Yes |
Yes |
| reg_wdata[18] |
No |
No |
No |
| reg_wdata[19] |
Yes |
Yes |
Yes |
| reg_wdata[20] |
No |
No |
No |
| reg_wdata[21] |
Yes |
Yes |
Yes |
| reg_wdata[23:22] |
No |
No |
No |
| reg_wdata[24] |
Yes |
Yes |
Yes |
| reg_wdata[25] |
No |
No |
No |
| reg_wdata[26] |
Yes |
Yes |
Yes |
| reg_wdata[30:27] |
No |
No |
No |
| reg_wdata[31] |
Yes |
Yes |
Yes |
| reg_en |
Yes |
Yes |
Yes |
| reg_we |
Yes |
Yes |
Yes |
| reg_rdata[2:0] |
Yes |
Yes |
Yes |
| reg_rdata[6:3] |
No |
No |
No |
| reg_rdata[7] |
Yes |
Yes |
Yes |
| reg_rdata[31:8] |
No |
No |
No |
| data_a[7:0] |
Yes |
Yes |
Yes |
| addr_a[1:0] |
Yes |
Yes |
Yes |
| valid_a |
Yes |
Yes |
Yes |
| ready_a |
Yes |
Yes |
Yes |
| data_b[7:0] |
Yes |
Yes |
Yes |
| addr_b[1:0] |
Yes |
Yes |
Yes |
| valid_b |
Yes |
Yes |
Yes |
| ready_b |
Yes |
Yes |
Yes |